The present invention relates to an insulated gate semiconductor device and more particularly, to a low on resistance device having minority carrier injection.
Insulated gate semiconductor devices possess the desirable feature of having a high impedance gate which simplifies gate drive circuitry. Insulated gate semiconductor devices can serve as high current, high power switches. Such devices as insulated gate bipolar transistors (IGBTs) are widely available. An N-channel power insulated gate device, for example, comprises a body of semiconductor material having a top surface containing a highly doped N-type conductivity source region, a moderately doped P-type conductivity base region and a moderately to lightly doped N-type conductivity drift region. The drift region is formed on a highly doped P-type conductivity anode region for an IGBT. The anode region is also referred to as a collector or a drain region. The anode region forms a bottom surface of the semiconductor body. Source and anode electrodes are attached to the source and anode regions, respectively, for coupling to external circuitry for carrying load current that flows through the device.
The drift region has relatively high resistivity to support high breakdown voltages. This high resistivity increases on resistance of the device during forward conduction, however. IGBTs use a P-type anode which provides a PN junction at the interface between the anode region and the drift region. This PN junction becomes forward biased when anode potential is greater than source potential by more than about 0.7 volts, and the PN junction injects minority carriers into the drift region, increasing conductivity and lowering on resistance. Unfortunately, the drift region is relatively thick, so minority carrier injection from the bottom of the drift region improves conductivity primarily in a lower portion of the drift region. Only a small percentage of the injected minority carriers reach an upper surface of the semiconductor body; on resistance remains high in the upper portion of the drift region.
Conventionally, the base region is electrically shorted to the source region to prevent activation of a parasitic bipolar transistor formed by the source which acts as an emitter, the base region which acts as a base, and the drift region which acts as a collector. Because the base to source PN junction was shorted it could not became forward biased during conduction, therefore it could not provide minority carrier injection into the upper portion of the drift region. A DMOS design described in U.S. Pat. No. 4,743,952 issued to B. J. Baliga provides separate hole injection regions in the upper surface of the drift region. These hole injection regions, however, were biased from a potential at the upper surface of the drift region. Potential at the upper surface is a very small potential in a properly designed MOS device. An insulated gate device structure is needed having a self biased means for conductivity modulating the upper portion of the drift region.